Buffering and interleaving data transfer between a chipset and memory modules

ABSTRACT

Providing electrical isolation between the chipset and the memory data is disclosed. The disclosure includes providing at least one buffer in a memory interface between a chipset and memory modules. Each memory module includes a plurality of memory ranks. The buffers allow the memory interface to be split into first and second sub-interfaces. The first sub-interface is between the chipset and the buffers. The second sub-interface is between the buffers and the memory modules. The method also includes interleaving output of the buffers, and configuring the buffers to properly latch the data being transferred between the chipset and the memory modules. The first and second sub-interfaces operate independently but in synchronization with each other.

BACKGROUND

[0001] The present disclosure relates to providing data buffers in aninterface between a chipset and multiple ranks of memory modules.

[0002] Computer systems often contain one or more integrated circuit(“IC”) chips, often called a chipset, that are coupled to memory modulesvia a memory interface. The memory interface provides communicationbetween the IC chipset (e.g. the CPU) and the memory modules. The memoryinterface may contain address bus lines, command signal lines, and databus lines. Increasing demand for higher computer performance andcapacity has resulted in a demand for a larger and faster memory.However, as the operating speed and the number of memory modulesconnected to the chipset increase, the resulting increased capacitiveloading may place a substantial limit on the amount and speed of memory.

[0003] Prior art designs, such as a registered dual in-line memorymodule (DIMM), have addressed the above-described difficulties byproviding an address/command buffer in the address bus lines and thecommand signal lines to relieve the capacitive loading effects.Karabatsos (U.S. Pat. No. 5,953,215) describes a loading relief designfor the data bus lines by providing FET switches in the interfacebetween the chipset and the memory modules.

[0004] In the prior art design 100 of FIG. 1, the interface 108 betweenthe chipset 102 and the memory modules 104 is unbuffered. In someembodiments, the memory modules 104 may be individually mounted onmemory boards 106 as shown. In other embodiments, the memory modules 104may be soldered directly onto the same motherboard as the chipset 102.

[0005] In the prior art design 100, the chipset 102 is often configuredto receive two supply voltages, about 1.0 volt (low) and 1.5 volts(high). The high voltage is necessary on the chipset side to providecompatible driving voltage on the memory interface 108. Further, the pincount on the chipset 102 may be designed to be 2x in order to provide aparticular memory access rate or frequency, such as ω.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Different aspects of the disclosure will be described inreference to the accompanying drawings wherein:

[0007]FIG. 1 shows a prior art design of an interface between a chipsetand memory modules;

[0008]FIG. 2 illustrates an embodiment of an interface having aplurality of data buffers disposed between the chipset and the memorymodules;

[0009]FIG. 3 shows a layout configuration of a data buffer;

[0010]FIG. 4 shows an alternative embodiment of the interface where eachmemory board contains multiple ranks of memory modules;

[0011]FIG. 5 is a front view of the interface showing the details ofmemory boards having multiple ranks of memory modules; and

[0012]FIG. 6 shows a method for buffering the data passed between thechipset and multiple ranks of memory modules.

DETAILED DESCRIPTION

[0013] The inventors of the present disclosure recognized that none ofthe prior art designs offer isolation of supply voltages and interfacescoupled to the chipset and the memory modules. Buffering the address andcommand lines relieves the capacitive loading effects, while providingthe FET switches in the data lines offers a loading relief on thoselines. However, neither design provides electrical isolation between thechipset and the memory data.

[0014] The differences in fabrication process between the chipset andthe memory modules place additional burdens on the computer systemdesign. For example, oxides on a memory chip are designed to be thick toprovide capacitors with good retention characteristic. Thick oxides alsokeep leakage current low. However, a higher voltage (on the order ofabout 1.2 to 1.8 volts) must be supplied to build conducting channelsbeneath the oxides. The chipset (Central Processing Unit (CPU) orapplication specific integrated circuit (ASIC) design) fabricationprocess, on the other hand, promotes thinner oxides providing fastertransistors. Therefore, the chipset may be operated at a lower voltage,typically less than 1.0 volt.

[0015] The present disclosure describes methods and systems forproviding electrical isolation between the chipset and the memory data.The method includes providing at least one buffer in a memory interfacebetween a chipset and memory modules. Each memory module includes aplurality of memory ranks. The buffer allows the memory interface to besplit into first and second sub-interfaces. The first sub-interface isbetween the chipset and the buffer. The second sub-interface is betweenthe buffer and the memory modules. The method also includes interleavingthe outputs of the memory ranks in the memory modules, and configuringthe buffers to properly latch data being transferred between the chipsetand the memory modules. The first and second sub-interfaces operateindependently but in synchronization with each other.

[0016] Buffering provides isolation of voltages and interfaces coupledto each of the chipset and the memory modules. The isolation of voltagesallows the chipset to be operated with a low operating voltage, whichsubstantially precludes the need for the chipset to have a highervoltage common with a memory supply voltage. The memory module is thenallowed to operate at voltages appropriate for its own operationalpurpose. The voltages may be independent of the operating voltage at theconnecting system (chipset).

[0017] The isolation of the interfaces allows the inherently fasterchipset interface to run at higher multiples of the memory interfacerate. For example, the chipset to data buffer interface may run at twicethe rate of the buffer to memory interface. This may allow the chipsetto operate at twice the rate and access the same amount of data withhalf the number of data bus lines or pins. This provides computer systemdesigners with a flexibility of utilizing a wider range of memory typesand interfaces for a particular computer system. By providing a databuffer on the memory module itself, the memory interface may besimplified by providing a short, fixed length stubs from the buffer tothe memory module. In some configurations, the data buffer may beprovided on the same motherboard as the chipset. An advantage providedby the electrical isolation that leads to the reduction in the pin countis illustrated in the design comparison between FIGS. 1 and 2.

[0018] Further, by providing more than one buffer on a memory board, theoutputs of memory ranks from one memory module may be interleaved withthat of another memory module on the same memory board. This allows theflexibility of designing a memory board with different size andconfiguration of the memory chips.

[0019] In the illustrated embodiment 200 of FIG. 2, a plurality of databuffers 206 is disposed in the memory interface between the chipset 202and the memory modules 204 to provide electrical isolation. For theillustrated embodiment, a multidrop bus 208 provides the interfacebetween the chipset 202 and the data buffers 206. The interface betweenthe chipset 202 and the data buffers 206 may be run at twice the dataaccess rate or frequency (2ω) as before, but with half the pin count (x)of the prior art design. The interface between the data buffers 206 andthe memory modules 204 still has 2x number of pins to provide the samedata access rate as before. In practice, x is often selected to be 16 or32. Moreover, the chipset 202 is configured to operate with only the lowvoltage (1.0 volt) as shown. The chipset 202 may be operated with lessthan 1.0 volt. The memory modules 204 are operated with only the highvoltage (1.5 volts). Typically, the memory modules 204 may be operatedwith voltages between 1.2 and 1.8 volts.

[0020] In the illustrated embodiment of FIG. 2, the data buffer 206 isprovided on the same memory board 210 as the memory module 204. However,the data buffer 206 may be provided on the motherboard containing thechipset 202.

[0021]FIG. 3 shows a layout configuration of a data buffer 300, similarto the data buffer 206 of FIG. 2, in accordance with an embodiment ofthe present disclosure. The data buffer 300 includes three portions 302,304, 306. The first portion 302 is a chipset input/output (I/O) portconfigured to send and receive data to and from the chipset through themultidrop bus 208. The first portion 302 operates at the same voltage(<1.0 volts) as the chipset. This allows compatibility of interfacebetween the chipset and the data buffer 300. The second portion 304 is acore data path logic portion allowing for buffering of data between thechipset and the memory module. The third portion 306 is a memory I/Oport configured to send and receive data to and from the memory module.The third portion operates at the same nominal voltage as the memorymodule (between 1.2 and 1.8 volts).

[0022]FIG. 4 shows an alternative embodiment 400 of FIG. 2, where eachmemory module 404, 405 contains two memory ranks 402. However, eachmemory module 404, 405 may include more than two memory ranks 402. Asbefore, the pin count on the interface between the chipset and thebuffer may be configured to be x while the pin count on the interfacebetween the buffer and the memory module 404, 405 is 2x.

[0023] Each buffer 408, 410 receives the outputs from the multiplememory ranks 402 within a memory module 404, 405. Thus, outputs from onememory module are routed to a respective buffer 408, 410. The dataoutputs from the buffers 408, 410 may then be interleaved before beingplaced on a multidrop bus. In the illustrated configuration, the bufferdata outputs are interleaved in a wired-OR configuration. The outputsmay be interleaved in different configurations such as in multiplexing.

[0024] The data outputs from the two buffers 408, 410 are thensequentially placed onto the multidrop bus 412. Control logic in thechipset may coordinate the transfer of data from the buffers 408, 410 inan interleaved mode. Thus in this embodiment, the two ranks 402 of thememory modules 404, 405 are bit-wise configured to double the bitnumbers required on the data buffer to the chipset interface.

[0025] A front view of the memory interface showing the details of thememory boards 502 is shown in FIG. 5. The figure also highlights theconnections to the data bus 512 and the data buffers 504. The front viewof the memory interface shows the isolation of the memory modules 510from the chipset 508. In the illustrated embodiment 500, the reductionin the pin count can be ascertained. For example, there are two linescoming from each memory module 510 to connect to each data buffer 504.However, there is only one line between the buffer 504 and the data bus512. Thus, in this case, the pin count may be reduced in half. Eachsolid line, between the memory modules 510 and the data buffer 504 andbetween the data buffer 504 and the data bus 512, may be implementedwith more than one electrically connecting line.

[0026] The embodiment 500 of FIG. 5 further illustrates the possibilityof having multiple data buffers 504 and memory modules 510, where eachmemory module 510 may have multiple memory ranks 506. In this embodiment500, a data buffer 504 is paired with one memory module 510 havingmultiple memory ranks 506. However, a data buffer 504 may be coupled tomore than one memory module 510.

[0027] This embodiment 500 also illustrates interleaving of the databuffer outputs to the data bus 512. For example, the output of the databuffer #1 may be coupled to the output of the data buffer #2 in awired-OR configuration. As stated above, control logic may coordinatethe transfer of data from the buffers 504 to the chipset 508 in aninterleaved mode.

[0028] The memory modules in this and other embodiments may be of anymemory types. However, in particular, the memory modules may be dynamicrandom access memories (DRAM), double data rate (DDR) DRAM, or quad datarate (QDR) DRAM. The quad data rate DRAM may be achieved by providing apin count of 4x in the second sub-interface between the buffer and thememory module, and operating the first sub-interface between the bufferand the chipset at 4 times the rate of the second sub-interface (seeFIG. 2).

[0029]FIG. 6 shows buffering the data passed between the chipset and aplurality of memory ranks in the memory modules. The buffers provideisolation of voltages and interfaces. The method includes providing atleast one buffer in an interface between a chipset and the multipleranks of memory modules at 600. The buffers allow the memory interfaceto be split into two interfaces. The first interface is between thechipset and the buffers. The second interface is between the buffers andthe multiple ranks of memory modules. The buffers provide isolationbetween the memory modules and the chipset. Outputs of the buffers arethen provided to the data bus by interleaving the outputs in a wired-ORconfiguration at 602. The buffer is then configured to properly latchthe data being transferred between the chipset and the plurality ofmemory modules at 604. This allows the first and second interfaces tooperate independently but synchronized with each other.

[0030] While specific embodiments of the invention have been illustratedand described, other embodiments and variations are possible. Forexample, although an illustrated embodiment shows only two memory ranksin a memory module, each rank providing one data line to a data buffer,the memory module may be configured to with more than two memory ranks.Furthermore, each memory rank may be implemented with more than one dataline to carry the data between the memory module and the buffer.

[0031] All these are intended to be encompassed by the following claims.

What is claimed is:
 1. A method, comprising: providing at least onebuffer in a memory interface between a chipset and a plurality of memorymodules, each module having a plurality of memory ranks, said at leastone buffer allowing the memory interface to be split into first andsecond sub-interfaces, where the first sub-interface is between thechipset and said at least one buffer, and the second sub-interface isbetween said at least one buffer and the memory modules, such that saidat least one buffer provides electrical isolation between the chipsetand the memory modules; configuring said at least one buffer to latchdata being transferred between the chipset and the memory modules, suchthat the first and second sub-interfaces operate independently but insynchronization with each other; and interleaving outputs of said atleast one buffer.
 2. The method of claim 1, wherein interleaving allowsbit numbers required on said second sub-interface to double.
 3. Themethod of claim 1, wherein providing at least one buffer isolates thefirst and second sub-interfaces in such a manner that the firstsub-interface is operated at different voltage level than the secondsub-interface.
 4. The method of claim 3, wherein an operating voltagelevel of said first sub-interface is less than 1.0 volt.
 5. The methodof claim 3, wherein an operating voltage level of said secondsub-interface is between 1.2 and 1.8 volts.
 6. The method of claim 1,wherein providing at least one buffer isolates the first and secondsub-interfaces in such a manner that the first sub-interface is operatedat a higher frequency than the second sub-interface.
 7. The method ofclaim 6, wherein said first sub-interface is operated at twice thefrequency of the second sub-interface.
 8. The method of claim 7, whereina number of data lines in said first sub-interface is half that of anumber of data lines in said second sub-interface.
 9. The method ofclaim 1, wherein interleaving outputs of said at least one buffer isprovided by connecting the outputs together in a wired-OR mode, andsequentially reading data from the buffer onto a data bus connected tothe chipset.
 10. The method of claim 1, wherein interleaving outputs ofsaid at least one buffer is provided by multiplexing the outputs, andsequentially outputting data onto a data bus.
 11. The method of claim 1,further comprising: providing a control logic to coordinate the transferof data from said at least one buffer in an interleaved mode.
 12. Themethod of claim 1, wherein each of said memory modules includes dynamicrandom access memory (DRAM).
 13. The method of claim 1, wherein each ofsaid memory modules includes double data rate (DDR) DRAM.
 14. The methodof claim 1, wherein each of said memory modules includes quad data rate(QDR) DRAM.
 15. A method, comprising: isolating a memory interfacebetween a chipset and at least one memory module, each memory modulecontaining a plurality of memory ranks, where isolating divides thememory interface into first and second sub-interfaces; configuring saidfirst and second sub-interfaces to transfer data between the chipset andsaid at least one memory module, such that the first and secondsub-interfaces operate independently but in synchronization with eachother; and interleaving outputs of said plurality of memory ranks, wheresaid first and second sub-interfaces are configured in such a mannerthat the first sub-interface is operated at a different voltage leveland at a higher frequency than the second sub-interface.
 16. The methodof claim 15, wherein said isolating a memory interface is provided by atleast one buffer disposed between said chipset and said at least onememory module.
 17. The method of claim 15, wherein an operating voltagelevel of said first sub-interface is less than 1.0 volt, and anoperating voltage level of said second sub-interface is between 1.2 and1.8 volts.
 18. The method of claim 15, wherein said first sub-interfaceis operated at twice the frequency of the second sub-interface.
 19. Themethod of claim 18, wherein a number of data lines in said firstsub-interface is half that of a number of data lines in said secondsub-interface.
 20. A system, comprising: a chipset; at least one memorymodule, each module including a plurality of memory ranks; a memoryinterface between said chipset and said at least one memory module; atleast one buffer disposed in said memory interface to divide said memoryinterface into first and second sub-interfaces, where said first andsecond sub-interfaces are configured in such a manner that the firstsub-interface is operated at different voltage level and at higherfrequency than the second sub-interface, and where multiple outputs ofsaid at least one buffer are interleaved.
 21. The system of claim 20,further comprising: a control logic to sequentially read saidinterleaved outputs of said at least one buffer onto said memoryinterface.
 22. The system of claim 20, wherein an operating voltagelevel of said first sub-interface is less than 1.0 volt, and anoperating voltage level of said second sub-interface is between 1.2 and1.8 volts.
 23. The system of claim 20, wherein said first sub-interfaceis operated at twice the frequency of the second sub-interface.
 24. Thesystem of claim 23, wherein a number of data lines in said firstsub-interface is half that of a number of data lines in said secondsub-interface.